Memory devices require a plurality of inputs and outputs through which data enters and exits the memory cells contained therein. Included among the various inputs and outputs are command, addressing and data signals. These signals are used to identify and access data storage locations (e.g., memory cells) within the memory device. As the quantity of memory cells increases, the number of input signals necessary to uniquely identify a memory cell also increases. Specifically, an address bus includes a sufficiently large quantity of address lines for uniquely identifying each of the memory cells in the memory device. Therefore, as the quantity of memory cells increases on the memory device, the quantity of inputs necessary for accessing the memory cells also increases.
Furthermore, since each of the input and output signals needs to be externally accessible for interfacing with external components such as memory controllers and the like, the periphery around the memory device must remain sufficiently large to accommodate external interconnections (e.g., pins) that are coupled to the input and output signals. As is readily appreciated, an increase in the quantity of interconnection pins to adequately address or select an increased density of memory cells creates a conflict with design motivations of further circuit miniaturization and integration. Therefore, there is a need for a memory device interface architecture that reduces the quantity of external interconnections required for input and output signals without introducing significant delay in accessing the memory cells in a memory device.